1. Field of the Invention
The present invention relates to an apparatus for addressing a memory for temporarily storing image data or reading image data stored in a memory according to a JPEG (Joint Photographic Experts Group) or MPEG (Moving Picture Experts Group) signal compression and expansion process, and a method thereof, and more particularly, to an addressing apparatus in which a discrete cosine transform (DCT) block scan address generation function and a raster scan address generation function are integrated, and an addressing method therefor.
2. Background Art
In an exemplary image data compressor external image signals are converted to composite data by analog-to-digital converion, and the composite data is divided into luminance and chrominance components which are then divided into Y, Cr and Cb data. The Y, Cr and Cb data is stored in a memory according to a sequence of conversion where a memory address line is connected to the output of a raster scan address generator. At this time, a horizontal synchronizing signal controls the change from one raster line to the next raster line, and a vertical synchronizing signal indicates the ending of a field or a frame. When an image data compressor performs the DCT with respect to the data stored in the memory, the data stored in the memory is read in a sequence of 8.times.8 blocks (or 4.times.4 blocks), where the memory address line is connected to the output of a separate block scan address generator. An exemplary image data decoder decodes the compressed data in a sequence reverse to that of the compressing process. That is, memory address lines are connected to the output of a block scan address generator for an image data decoder to decode the compressed data, and the memory address lines are connected to the output of a separate raster scan address generator for a luminance/chrominance combiner to combine the luminance and chrominance data into composite data. The combined data is then converted to an image signal using digital-to-analog conversion. Accordingly, two address generators are required according to the above-described sequences of raster scan and block scan, to thereby require a great deal of hard wares, which complicates the design of the hardware, and thus increases the total cost.
Another example of image signal compression and expansion using DCT is contemplated by Kenji Kishi in U.S. Pat. No. 5,563,662 entitled Image Signal Compressing and Expansion With Filter Means To Eliminate Blocking Effect wherein resulting DCT coefficients are subjected to quantization and Hoffman coding prior to storage in a memory as compressed image data and decoded in reverse using Hoffman decoding and inverse quantization to generate decoded DCT coefficients which are input to an inverse discrete cosine transform circuit to be converted to an image signal which is then filtered and differentiated to remove deformation caused by boundaries between blocks.